The invention lies in the field of semiconductor processing and relates, more specifically, to a method for fabricating a semiconductor wafer using multiple exposure.
Integrated semiconductor circuits are generally fabricated with lithographic processing of a mask in order to transfer the structure into the underlying layers of the semiconductor wafer in a subsequent process step, e.g. with the aid of an etching or an implantation process step. In this case, the mask generally comprises a thin radiation-sensitive layer, usually an organic photoresist layer, which is deposited on the semiconductor wafer. This thin radiation-sensitive layer is then irradiated in the desired regions, the irradiation generally being effected optically with the aid of a photomask. The photoresist layer that has been chemically altered by the radiation is then developed. In positive resist technology, the photoresist decomposes at the exposed locations and the non-irradiated regions remain masked. In negative resist technology, in precisely the opposite fashion, the exposed locations are marked, while the unexposed resist is removed during development. The resulting pattern in the photoresist layer serves as a mask for the subsequent process step by means of which this pattern is then transferred into the underlying layers in the semiconductor wafer.
On account of the increasing miniaturization of the integrated circuits, it is necessary to image ever smaller structures with feature sizes below 100 nm on the photoresist layer and then to transfer this pattern into the underlying layers of the semiconductor wafer. The lithographic production of such small structures is difficult particularly in regions with a dense arrangement of structures with dimensions in the region of the resolution limit of the optical exposure methods.
Accordingly, minimum feature size and pitch are driving the use of multiple lithography exposures and multiple etches to create a pattern which previously could be done with only one exposure and one etch. Such multiple lithography exposure and etch process steps give rise to many issues.